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19-3945; Rev 1; 7/06
IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs
General Description
The MAX5953A/MAX5953B/MAX5953C/MAX5953D integrate a complete power IC solution for Powered Devices (PD) in a Power-Over-Ethernet (PoE) system, in compliance with the IEEE 802.3af standard. The MAX5953A/MAX5953B/MAX5953C/MAX5953D provide the PD with a detection signature, a classification signature, and an integrated isolation switch with programmable inrush current control. These devices also integrate a voltage-mode PWM controller with two power MOSFETs connected in a two-switch voltageclamped DC-DC converter configuration. An integrated MOSFET provides PD isolation during detection and classification. All devices guarantee a leakage current offset of less than 10A during the detection phase. A programmable current limit prevents high inrush current during power-on. The devices feature power-mode undervoltage lockout (UVLO) with wide hysteresis and long deglitch time to compensate for twisted-pair-cable resistive drop and to assure glitch-free transition between detection, classification, and power-on/-off phases. The MAX5953A/MAX5953C have an adjustable UVLO threshold with the default value compliant to the 802.3af standard, while the MAX5953B/MAX5953D have a lower and fixed UVLO threshold compatible with some legacy pre-802.3af power-sourcing equipment (PSE) devices. The DC-DC converters are operable in either forward or flyback configurations with a wide input voltage range from 11V to 76V and up to 15W of output power. The voltage-clamped power topology enables full recovery of stored magnetizing and leakage inductive energy for enhanced efficiency and reliability. When using the high-side MOSFET, the controller can be configured as a buck converter. A look-ahead signal for driving secondary-side synchronous rectifiers can be used to increase efficiency. A wide array of protection features include UVLO, over-temperature shutdown, and shortcircuit protection with hiccup current limit for enhanced performance and reliability. Operation up to 500kHz allows for smaller external magnetics and capacitors. The MAX5953A/MAX5953B/MAX5953C/MAX5953D are available in a high-power (2.22W), 7mm x 7mm thermally enhanced thin QFN package.
Features
Powered Device Interface Fully Integrated IEEE 802.3af-Compliant PD Interface PD Detection and Programmable Classification Signatures Less than 10A Leakage Current Offset During Detection Integrated MOSFET for Isolation and Inrush Current Limiting Gate Output Allows External Control of the Internal Isolation MOSFET Programmable Inrush Current Control Programmable Undervoltage Lockout (MAX5953A/MAX5953C) DC-DC Converter Clamped, Two-Switch Power IC for High Efficiency Integrated High-Voltage 0.4 Power MOSFETs Up to 15W Output Power Bias Voltage Regulator with Automatic HighVoltage Supply Turn-Off 11V to 76V Wide Input Voltage Range Feed-Forward Voltage-Mode Control for Fast Input Transient Rejection Programmable Undervoltage Lockout Overtemperature Shutdown Indefinite Short-Circuit Protection with Programmable Fault Integration Integrated Look-Ahead Signal for SecondarySide Synchronous Rectification > 90% Efficiency with Synchronous Rectification Up to 500kHz Switching Frequency High-Power (2.22W), 7mm x 7mm Thermally Enhanced Lead-Free Thin QFN Package
MAX5953A/MAX5953B/MAX5953C/MAX5953D
Ordering Information
PART MAX5953AUTM+ MAX5953BUTM+ MAX5953CUTM+ MAX5953DUTM+ PIN-PACKAGE 48 TQFN 48 TQFN 48 TQFN 48 TQFN PKG CODE T4877-6 T4877-6 T4877-6 T4877-6
Applications
IEEE 802.3af Powered Devices IP Phones Wireless Access Nodes Internet Appliances Security Cameras Computer Telephony
Operating junction temperature range is 0C to +125C. +Denotes lead-free package.
Pin Configuration and Typical Operating Circuit appear at end of data sheet. 1
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs MAX5953A/MAX5953B/MAX5953C/MAX5953D
ABSOLUTE MAXIMUM RATINGS
V+ to VEE ................................................................-0.3V to +90V OUT, PGOOD, PGOOD to VEE .....................-0.3V to (V+ + 0.3V) RCLASS, GATE to VEE ...........................................-0.3V to +12V UVLO to VEE ............................................................ -0.3V to +8V PGOOD to OUT ........................................... -0.3V to (V+ + 0.3V) HVIN, INBIAS, DRNH, XFRMRH, XFRMRL to GND.................................................-0.3V to +80V BST to GND ........................................................... -0.3V to +95V BST to XFRMRH .................................................... -0.3V to +12V PGND to GND .......................................................-0.3V to +0.3V DCUVLO, RAMP, CSS, OPTO, FLTINT, RCFF, RTCT to GND..................................................... -0.3V to +12V SRC, CS to GND...................................................... -0.3V to +6V REGOUT, DRVIN to GND .......................................-0.3V to +12V REGOUT to HVIN .................................................. -80V to +0.3V REGOUT to INBIAS ............................................... -80V to +0.3V PPWM to GND....................................-0.3V to (VREGOUT + 0.3V) *As per JEDEC 51 standard.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Maximum Input/Output Current (Continuous) OUT to VEE ....................................................................500mA V+, RCLASS to VEE .........................................................70mA UVLO, PGOOD, PGOOD to VEE .....................................20mA GATE to VEE ....................................................................80mA REGOUT to GND ............................................................50mA DRNH, XFRMRH, XFRMRL, SRC to GND (Average), TJ = +125C..................................................................0.9A PPWM to GND ..............................................................20mA Continuous Power Dissipation* (TA = +70C) 48-Pin TQFN 7mm X 7mm (derate 27.8mW/C above +70C) .............................2222mW JA ................................................................................36C/W Operating Ambient Temperature Range ................0C to +85C Operating Junction Temperature Range ..............0C to +125C Junction Temperature ......................................................+150C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10s) .................................+300C
ELECTRICAL CHARACTERISTICS
(VIN = (V+ - VEE) = 48V, GATE = PGOOD = PGOOD = unconnected, GND = OUT, HVIN = V+, UVLO = VEE, TJ = 0C to +125C, unless otherwise noted. Typical values are at TJ = +25C. All voltages are referenced to VEE, unless otherwise noted.) (Note 1)
PARAMETER DETECTION MODE Input Offset Current Effective Differential Input Resistance (Note 3) CLASSIFICATION MODE Classification Current Turn-Off Threshold VTH,CLASS VIN rising (Note 4) VIN = 12.6V to 20V, RDISC = 25.5k (Notes 5, 6) Class 0, RRCLASS = 10k Class 1, RRCLASS = 732 Class 2, RRCLASS = 392 Class 3, RRCLASS = 255 Class 4, RRCLASS = 178 20.8 0 9.17 17.29 26.45 36.6 21.8 22.5 2 11.83 19.71 29.55 41.4 67 0.4 37.4 34.3 30 38.6 35.4 1 40.2 36.9 V mA V V mA V IOFFSET dR VIN = 1.4V to 10.1V (Note 2) VIN = 1.4V, up to 10.1V with 1V step 550 10 A k SYMBOL CONDITIONS MIN TYP MAX UNITS
POWERED DEVICE (PD) INTERFACE
Classification Current
ICLASS
POWER MODE Operating Supply Voltage Operating Supply Current Default Power Turn-On Voltage Default Power Turn-Off Voltage VIN IIN VUVLO, ON VUVLO,OFF VIN = (V+ - VEE) Measure at V+, not including RDISC, GATE = VEE, HVIN = GND = OUT VIN increasing MAX5953A/MAX5953C MAX5953B/MAX5953D
VIN decreasing, MAX5953A/MAX5953C
2
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IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs
ELECTRICAL CHARACTERISTICS (continued)
(VIN = (V+ - VEE) = 48V, GATE = PGOOD = PGOOD = unconnected, GND = OUT, HVIN = V+, UVLO = VEE, TJ = 0C to +125C, unless otherwise noted. Typical values are at TJ = +25C. All voltages are referenced to VEE, unless otherwise noted.) (Note 1)
PARAMETER Default Power Turn-On/Off Hysteresis Voltage External UVLO Programming Range UVLO External Reference Voltage UVLO External Reference Voltage Hysteresis UVLO Bias Current UVLO Input Ground-Sense Threshold UVLO Input Ground-Sense Glitch Rejection Power Turn-Off Voltage, Undervoltage Lockout Deglitch Time Isolation Switch n-Channel MOSFET On-Resistance Isolation Switch n-Channel MOSFET Off-Threshold Voltage GATE Pulldown Switch Resistance GATE Charging Current GATE High Voltage PGOOD Assertion VOUT Threshold (Note 10) PGOOD, PGOOD Assertion VGATE Threshold PGOOD, PGOOD Output Low Voltage PGOOD Leakage Current PGOOD Leakage Current tOFF_DLY VIN, VUVLO falling (Note 9) Output current = 300mA, VGATE = 5.6V, measured between OUT and VEE VGATE - VEE, OUT = V+, output current < 1A Power-off mode, VIN = +12V VGATE = 2V IGATE = 1A VOUT - VEE decreasing, VGATE = 5.75V Hysteresis VGATE - VEE increasing Hysteresis ISINK = 2mA, VOUT (V+ - 5V) (Note 11) GATE = high, V+ - VOUT = 67V (Note 11) GATE = VEE, PGOOD - VEE = 67V (Note 11) 4.62 4.5 5.59 1.16 0.5 38 10 5.76 1.23 70 4.76 80 0.2 1 1 4.91 80 16.5 5.93 1.31 0.32 SYMBOL VHYST,UVLO VIN,EX VREF,UVLO VHYST,UVLO IIN,UVLO VTH,G,UVLO CONDITIONS MAX5953A/MAX5953C MAX5953B/MAX5953D MAX5953A/MAX5953C only (Note 7) VUVLO increasing Ratio to VREF, UVLO VUVLO = 2.460V (Note 8) MIN 7.1 4 12 2.400 19.2 -1.5 50 7 2.460 20 67 2.522 20.9 +1.5 440 TYP MAX UNITS V V V % A mV s
MAX5953A/MAX5953B/MAX5953C/MAX5953D
ms
RON,ISO VGSTH RG IGATE VGATE VOUTEN VGSEN VOL,PGOOD
0.6
1.5
V A V V mV V mV V A A
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3
IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs MAX5953A/MAX5953B/MAX5953C/MAX5953D
ELECTRICAL CHARACTERISTICS (DC-DC Controller)
(All voltages referenced to GND, unless otherwise noted. VHVIN = +48V, CINBIAS = 1F, CREGOUT = 2.2F, RRTCT = 25k, CRTCT = 100pF, CBST = 0.22F, VCSS = VCS = 0V, VRAMP = VDCUVLO = 3V, TJ = 0C to +125C, unless otherwise noted. Typical values are at TJ = +25C, unless otherwise noted.) (Note 1)
PARAMETER Input Supply Range OSCILLATOR (RTCT) PWM Frequency Maximum PWM Duty Cycle Maximum RTCT Frequency RTCT Peak Trip Level RTCT Valley Trip Level RTCT Input Bias Current RTCT Discharge MOSFET RDS(ON) RTCT Discharge Pulse Width LOOK-AHEAD LOGIC (PPWM) PPWM to Output Propagation Delay PPWM Output High PPWM Output Low Common-Mode Input Range Input Offset Voltage Input Bias Current RAMP to XFRMRL Propagation Delay Minimum OPTO Voltage Minimum RCFF Voltage REGOUT LDO (REGOUT) REGOUT Voltage Set Point VREGOUT INBIAS unconnected, VHVIN = 11V to 76V VINBIAS = VHVIN = 11V to 76V INBIAS unconnected, VHVIN = 15V, IREGOUT = 0 to 30mA VINBIAS = VHVIN = 15V, IREGOUT = 0 to 30mA REGOUT Dropout Voltage REGOUT Undervoltage Lockout Threshold REGOUT Undervoltage Lockout Threshold Hysteresis INBIAS unconnected, IREGOUT = 30mA VINBIAS = VHVIN, IREGOUT = 30mA REGOUT rising REGOUT falling 6.6 7.0 0.7 8.3 9.5 8.75 10.6 9.2 11.0 0.25 V 0.25 1.25 1.25 7.4 V V V V tCOMPARATOR From VRAMP (50mV overdrive) rising to VXFRMRL rising VCSS = 0V, OPTO sinking 2mA RCFF sinking 2mA -2 100 1.47 2.18 tPPWM VOH,PPWM VOL,PPWM VCM_PWM VPPWM rising to VXFRMRL falling Sourcing 2mA Sinking 2mA 0 10 +2 7.0 110 11.0 0.2 5.5 ns V V V mV A ns V V fS DMAX fRTCTMAX VTH,RTCT VTL,RTCT IIN,RTCT RDIS,RTCT Sinking 50mA (Note 12) 250 47 1 0.51 x VREGOUT 1 1 35 50 85 kHz % MHz V V A ns SYMBOL VHVIN CONDITIONS MIN 11 TYP MAX 76 UNITS V
PWM COMPARATOR (OPTO, RAMP, RCFF)
REGOUT Load Regulation
4
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IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs
ELECTRICAL CHARACTERISTICS (DC-DC Controller) (continued)
(All voltages referenced to GND, unless otherwise noted. VHVIN = +48V, CINBIAS = 1F, CREGOUT = 2.2F, RRTCT = 25k, CRTCT = 100pF, CBST = 0.22F, VCSS = VCS = 0V, VRAMP = VDCUVLO = 3V, TJ = 0C to +125C, unless otherwise noted. Typical values are at TJ = +25C, unless otherwise noted.) (Note 1)
PARAMETER SOFT-START (CSS) Soft-Start Current INTEGRATING FAULT PROTECTION FLTINT Source Current FLTINT Trip Point FLTINT Hysteresis INTERNAL POWER FETs On-Resistance Off-State Leakage Current Total Gate Charge Per Power FET HIGH-SIDE DRIVER Low to High Latency High to Low Latency Output Drive Voltage LOW-SIDE DRIVER Low to High Latency High to Low Latency tLH-LS tHL-LS Driver delay until FET VGS reaches 0.9 x VDRVIN and is fully on Driver delay until FET VGS reaches 0.1 x VDRVIN and is fully off 80 40 ns ns tLH-HS tHL-HS VBST Driver delay until FET VGS reaches 0.9 x (VBST - VXFRMRH) and is fully on Driver delay until FET VGS reaches 0.1 x (VBST - VXFRMRH) and is fully off BST to XFRMRH with high side on 80 40 8 ns ns V RON,POWER VDRVIN = VBST = 9V, VXFRMRH = VSRC = 0V, IDS = 50mA -5 15 0.4 0.8 +10 A nC IFLTINT VFLTINT rising 80 2.7 0.75 A V V ICSS VCSS = 0V 33 A SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5953A/MAX5953B/MAX5953C/MAX5953D
CURRENT-LIMIT COMPARATOR (CS) Current-Limit Threshold Voltage Current-Limit Input Bias Current Propagation Delay to XFRMRL VILIM IBILIM tdILIM 0 < VCS < 0.3V From VCS rising (10mV overdrive) to VXFRMRL rising 140 -2 160 156 172 +2 mV A ns
BOOST VOLTAGE CIRCUIT (See Figure 9, QB) Driver Output Delay One-Shot Pulse Width QB RDSON THERMAL SHUTDOWN Shutdown Temperature Thermal Hysteresis TSH TH Temperature rising +160 20 C C tPPWMD tPWQB Sinking 20mA 200 300 30 60 ns ns
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5
IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs MAX5953A/MAX5953B/MAX5953C/MAX5953D
ELECTRICAL CHARACTERISTICS (DC-DC Controller) (continued)
(All voltages referenced to GND, unless otherwise noted. VHVIN = +48V, CINBIAS = 1F, CREGOUT = 2.2F, RRTCT = 25k, CRTCT = 100pF, CBST = 0.22F, VCSS = VCS = 0V, VRAMP = VDCUVLO = 3V, TJ = 0C to +125C, unless otherwise noted. Typical values are at TJ = +25C, unless otherwise noted.) (Note 1)
PARAMETER Threshold Voltage Hysteresis Input Bias Current SUPPLY CURRENT From VHVIN = 11V to 76V, VCSS = 0V, VINBIAS = 11V Supply Current From VINBIAS = 11V to 76V, VCSS = 0V, VHVIN = 76V From VHVIN = 76V, VOPIO = 4V Standby Supply Current VDCUVLO = 0V 0.7 4.4 7 1 mA 1.5 6.4 mA SYMBOL VREF,DCUVLO VHYS,DCUVLO IIN,DCUVLO VDCUVLO = 3V -100 CONDITIONS VDCUVLO rising MIN 1.14 TYP 1.26 140 +100 MAX 1.38 UNITS V mV nA
UNDERVOLTAGE LOCKOUT (DCUVLO)
Limits at 0C are guaranteed by design, unless otherwise noted. The input offset current is illustrated in Figure 1. Effective differential input resistance is defined as the differential resistance between V+ and VEE without any external resistance. Note 4: Classification current is turned off whenever the IC is in power mode. Note 5: See Table 2 in the Classification Mode section. RDISC and RRCLASS must be 1%, 100ppm or better. ICLASS includes the IC bias current and the current drawn by RDISC. Note 6: See the Thermal Dissipation section. Note 7: When UVLO is connected to the midpoint of an external resistor-divider with a series resistance of 25.5k (1%), the turnon threshold set point for the power mode is defined by the external resistor-divider. Make sure the voltage on UVLO does not exceed its maximum rating of 8V when VIN is at the maximum voltage. Note 8: When VUVLO is below VTH,G,UVLO, the MAX5953A/MAX5953C set the turn-on voltage threshold internally (VUVLO,ON). Note 9: An input voltage or VUVLO glitch below their respective thresholds shorter than or equal to tOFF_DLY does not cause the MAX5953A/MAX5953B/MAX5953C/MAX5953D to exit power-on mode (as long as the input voltage remains above an operable voltage level of 12V). Note 10: Guaranteed by design, not tested in production for MAX5953B/MAX5953D. Note 11: PGOOD references to OUT while PGOOD references to VEE. Note 12: Output switching frequency is 1/2 oscillator frequency.
IIN dRi 1V (VINi + 1 - VINi) = (IINi + 1 - IINi) (IINi + 1 - IINi) VINi dRi
Note 1: Note 2: Note 3:
IOFFSET IINi IINi + 1 IINi
dRi
IOFFSET VINi 1V VINi + 1 VIN
Figure 1. Effective Differential Input Resistance/Offset Current 6 _______________________________________________________________________________________
IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs
Typical Operating Characteristics
(VIN = (V+ - VEE) = 48V, GATE = PGOOD = unconnected, GND connected to OUT, HVIN connected to V+, UVLO = V EE, CINBIAS = 1F, CREGOUT = 2.2F, RRTCT = 25k, CRTCT = 100pF, CBST = 0.22F, TJ = 0C to +125C, unless otherwise noted. Typical values are at TJ = +25C. All voltages are referenced to VEE, unless otherwise noted.) CLASSIFICATION CURRENT EFFECTIVE DIFFERENTIAL INPUT DETECTION CURRENT vs. INPUT VOLTAGE RESISTANCE vs. INPUT CURRENT vs. INPUT VOLTAGE
MAX5953A/B/C/D toc02
MAX5953A/MAX5953B/MAX5953C/MAX5953D
RDISC = 25.5k DETECTION CURRENT (mA) 0.4 IIN + IRDISC 0.3
MAX5953A/B/C/D toc01
45 CLASSIFICATION CURRENT (mA) 40 35 30 25 20 15 10 5 CLASS 2 CLASS 1 CLASS 0 0 5 10 15 20 25 CLASS 3 CLASS 4
3.0 2.5 2.0 1.5 1.0 0.5 0 0 2 4 6 8
0.2
0.1
0 0 2 4 6 8 10 INPUT VOLTAGE (V)
0 30 INPUT VOLTAGE (V)
10
INPUT VOLTAGE (V)
INPUT OFFSET CURRENT vs. INPUT VOLTAGE
MAX5953A/B/C/D toc04
NORMALIZED UVLO vs. TEMPERATURE
1.008 1.006 NORMALIZED UVLO 1.004 1.002 1.000 0.998 0.996 0.994 50
MAX5953A/B/C/D toc05
PGOOD OUTPUT LOW VOLTAGE vs. CURRENT
MAX5953A/B/C/D toc06
0 -0.5 INPUT OFFSET CURRENT (A) -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 0 2 4 6 8
1.010
250
200 VPGOOD (mV)
150
100
0.992 10 0.990 0 25 50 75 100 125 TEMPERATURE (C) 0 0 5 10 ISINK (mA) 15 20
INPUT VOLTAGE (V)
OUT LEAKAGE CURRENT vs. TEMPERATURE
MAX5953A/B/C/D toc07
INRUSH CURRENT CONTROL (VIN = 48V)
VGATE 5V/div
DCUVLO THRESHOLD vs. TEMPERATURE
DCUVLO RISING 1.2800 VDCUVLO (V)
MAX5953A/B/C/D toc09
1000 VOUT = 48V OUT LEAKAGE CURRENT (nA) 100
MAX5953A/B/C/D toc08
1.2825
0V VOUT TO VEE 50V/div IINRUSH 100mA/div
10
0V
1.2775
1
0A
1.2750
0.1 0 25 50 75 100 125 TEMPERATURE (C)
PGOOD 50V/div 4ms/div
0V
1.2725 0 25 50 75 100 125 TEMPERATURE (C)
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7
MAX5953A/B/C/D toc03
0.5
50
EFFECTIVE DIFFERENTIAL INPUT RESISTANCE (M)
3.5
IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs MAX5953A/MAX5953B/MAX5953C/MAX5953D
Typical Operating Characteristics (continued)
(VIN = (V+ - VEE) = 48V, GATE = PGOOD = unconnected, GND connected to OUT, HVIN connected to V+, UVLO = VEE, CINBIAS = 1F, CREGOUT = 2.2F, RRTCT = 25k, CRTCT = 100pF, CBST = 0.22F, TJ = 0C to +125C, unless otherwise noted. Typical values are at TJ = +25C. All voltages are referenced to VEE, unless otherwise noted.) HVIN AND INBIAS INPUT CURRENT HVIN STANDBY CURRENT HVIN INPUT CURRENT vs. TEMPERATURE vs. TEMPERATURE vs. TEMPERATURE
MAX5953A/B/C/D toc10 MAX5953A/B/C/D toc11
350 315 STANDBY CURRENT (A) 280 245 210 175 140 105 70 35 0 0 25 50 75 100 fHVIN VDCUVLO = 0V
4.7 4.6 IHVIN (mA) 4.5 4.4 4.3 4.2 4.1 4.0
INBIAS FLOATING VHVIN = 76V REGOUT = DRVIN
4.5 4.0 INPUT CURRENT (mA) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0
VHVIN = VINBIAS = 76V
IINBIAS
IHVIN
125
0
25
50
75
100
125
0
25
50
75
100
125
TEMPERATURE (C)
TEMPERATURE (C)
TEMPERATURE (C)
REGOUT VOLTAGE vs. INPUT VOLTAGE
MAX5953A/B/C/D toc13
REGOUT VOLTAGE vs. TEMPERATURE
MAX5953A/B/C/D toc14
REGOUT VOLTAGE vs. LOAD CURRENT
VHVIN = 15V INBIAS FLOATING GND = VEE 8.80 VREGOUT (V)
MAX5953A/B/C/D toc15
8.85 8.84 8.83 8.82 VREGOUT (V) 8.81 8.80 8.79 8.78 8.77 8.76 8.75 11 24 37 50 63 INBIAS FLOATING GND = VEE
8.90 8.88 8.86 8.84 VREGOUT (V) 8.82 8.80 8.78 8.76 8.74 8.72 8.70 VHVIN = 48V INBIAS FLOATING
8.85
8.75
8.70
8.65 0 25 50 75 100 125 0 5 10 15 IREGOUT (mA) 20 25 30 TEMPERATURE (C)
76
VHIN (V)
REGOUT VOLTAGE vs. INPUT VOLTAGE
MAX5953A/B/C/D toc16
REGOUT VOLTAGE vs. TEMPERATURE
MAX5953A/B/C/D toc17
REGOUT VOLTAGE vs. LOAD CURRENT
VHVIN = VINBIAS = 15V GND = VEE
MAX5953A/B/C/D toc18
10.70 HVIN = INBIAS GND = VEE 10.68 VREGOUT (V)
10.75 10.74 10.73 10.72 VREGOUT (V) 10.71 10.70 10.69 10.68 VHVIN = VINBIAS = 48V
10.75
10.70 VREGOUT (V)
10.66
10.65
10.64
10.60
10.62
10.67 10.66
10.55
10.60 11 24 37 50 63 76 VHIN (V)
10.65 0 25 50 75 100 125 TEMPERATURE (C)
10.50 0 5 10 15 IREGOUT (mA) 20 25 30
8
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MAX5953A/B/C/D toc12
385
4.8
5.0
IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs
Typical Operating Characteristics (continued)
(VIN = (V+ - VEE) = 48V, GATE = PGOOD = unconnected, GND connected to OUT, HVIN connected to V+, UVLO = VEE, CINBIAS = 1F, CREGOUT = 2.2F, RRTCT = 25k, CRTCT = 100pF, CBST = 0.22F, TJ = 0C to +125C, unless otherwise noted. Typical values are at TJ = +25C. All voltages are referenced to VEE, unless otherwise noted.)
REGOUT UVLO VOLTAGE vs. TEMPERATURE
MAX5953A/B/C/D toc19
MAX5953A/MAX5953B/MAX5953C/MAX5953D
OPERATING FREQUENCY vs. TEMPERATURE
550 OPERATING FREQUENCY (kHz) 500 450 400 350 300 250 200 RRTCT = 24.3k CRTCT = 100pF RRTCT = 12k CRTCT = 100pF
MAX5953A/B/C/D toc20
SOFT-START CURRENT vs. TEMPERATURE
MAX5953A/B/C/D toc21
7.4 7.2 REGOUT UVLO VOLTAGE (V) 7.0 6.8 6.6 6.4 6.2 6.0 0 25 50 75 100 FALLING RISING
600
34.0 33.5 SOFT-START CURRENT (A) 33.0 32.5 32.0 31.5 31.0
125
0
25
50
75
100
125
0
25
50
75
100
125
TEMPERATURE (C)
TEMPERATURE (C)
TEMPERATURE (C)
MINIMUM RCFF AND OPTO LEVELS vs. TEMPERATURE
MAX5953A/B/C/D toc22
CURRENT-LIMIT COMPARATOR THRESHOLD vs. TEMPERATURE
HVIN RISING
MAX5953A/B/C/D toc23
PPWM TO XFRMRL SKEW vs. TEMPERATURE
99 PPWM TO XFRMRL SKEW (ns) 98 97 96 95 94 93 92 91 90
MAX5953A/B/C/D toc24
2.75 2.50 VRCFF (V), VOPTO (V) 2.25 2.00 1.75 1.50 1.25 1.00 0 25 50 75 100 OPTO RCFF
0.160 0.159 0.158 0.157 VREGOUT (V) 0.156 0.155 0.154 0.153 0.152 0.151 0.150
100
125
0
25
50
75
100
125
0
25
50
75
100
125
TEMPERATURE (C)
TEMPERATURE (C)
TEMPERATURE (C)
FLTINT CURRENT vs. TEMPERATURE
MAX5953A/B/C/D toc25
FLTINT SHUTDOWN VOLTAGE vs. TEMPERATURE
MAX5953A/B/C/D toc26
POWER MOSFETS RDS(ON) vs. TEMPERATURE
MAX5953A/B/C/D toc27
85 84 83 82 IFLTINT (A) 81 80 79 78 77 76 75 0 25 50 75 100
2.9 2.8 2.7 2.6 VFLTINT (V) 2.5 2.4 2.3 2.2 2.1 2.0 1.9 FALLING RISING
0.7 0.6 0.5 RDS(ON) () 0.4 0.3 0.2 0.1 0
125
0
25
50
75
100
125
0
25
50
75
100
125
TEMPERATURE (C)
TEMPERATURE (C)
TEMPERATURE (C)
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9
IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs MAX5953A/MAX5953B/MAX5953C/MAX5953D
Pin Description
PIN 1, 2, 3, 5, 7, 12, 13, 14, 17, 19, 35, 38, 46, 47, 48 4 NAME N.C. V+ FUNCTION No Connection. Not internally connected. Make no electrical connection to these pins. Positive Input Power. Referenced to VEE. Undervoltage Lockout Programming Input for PD Interface. UVLO is referenced to VEE. When UVLO is above its threshold, the device enters the power mode. Connect UVLO to VEE to use the default undervoltage lockout threshold. Connect UVLO to the center of an external resistor-divider between V+ and VEE to define a threshold externally. The series resistance value of the external resistors must add to 25.5k (1%) and replaces the detection resistor. To keep the device in undervoltage lockout, drive UVLO between VTH,G,UVLO and VREF,UVLO. No Connection. Not internally connected. Make no electrical connection to this pin. Classification Setting for PD Interface. RCLASS is referenced to VEE. Add a resistor from RCLASS to VEE to set a PD class (see Tables 1 and 2). Gate of Internal Isolation n-Channel Power MOSFET. GATE is referenced to VEE. GATE sources 10A when the device enters power mode. Connect an external 100V ceramic capacitor from GATE to OUT to program the inrush current. Drive GATE to VEE to turn off the internal MOSFET. The detection and classification functions operate normally when GATE is driven to VEE. Negative Input Power. Source of the integrated isolation n-channel power MOSFET. Output Voltage. OUT is referenced to VEE. OUT is connected to the drain of the integrated isolation n-channel power MOSFET. Connect OUT to GND. Active-High, Open-Drain Power-Good Indicator Output for PD Interface. PGOOD is referenced to OUT. PGOOD goes high impedance when VOUT is within 1.2V of VEE and when VGATE is 5V above VEE. Otherwise, PGOOD is internally pulled to OUT (given that VOUT is at least 5V below V+). PGOOD can be connected directly to CSS or DCUVLO to enable/disable the DC-DC converter. Active-Low, Open-Drain Power-Good Indicator Output for PD Interface. PGOOD is referenced to VEE. PGOOD is pulled to VEE when VOUT is within 1.2V of VEE and when VGATE is 5V above VEE. Otherwise, PGOOD goes high impedance. Current-Sense Input for PWM Controller. CS is referenced to PGND. The current-limit threshold is internally set to 156mV relative to PGND. The device has an internal noise filter. If necessary, connect an external RC filter from CS to PGND for additional filtering. PWM Pulse Output. Referenced to GND. PPWM leads the internal power MOSFET pulse by approximately 100ns. Signal Ground of PWM Controller. Connect GND to PGND. Power Ground of the DC-DC Converter Power Stage. Connect PGND to GND. Soft-Start Timing Capacitor Connection for PWM Controller. CSS is referenced to GND. Connect a 0.01F or greater ceramic capacitor from CSS to GND. Connect to PGOOD to automatically enable the PWM controller from the PD interface.
6 (MAX5953A/MAX5953C)
UVLO
6 (MAX5953B/MAX5953D) 8
N.C. RCLASS
9
GATE
10, 11 15, 16
VEE OUT
18 (MAX5953A/MAX5953B)
PGOOD
18 (MAX5953C/MAX5953D)
PGOOD
20
CS
21 22 23 24
PPWM GND PGND CSS
10
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IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs
Pin Description (continued)
PIN 25 26, 27 28, 29 30 31, 32 NAME OPTO SRC XFRMRL DRVIN XFRMRH FUNCTION PWM Comparator Inverting Input. OPTO is referenced to GND. Connect the collector of the optotransistor to OPTO and a pullup resistor to REGOUT. Source Connection of Low-Side Power MOSFET in the Two-Switch Power Stage of the DCDC Converter. Connect SRC to PGND with a low-value resistor for current limiting. Low-Side Connection for the Isolation Transformer. Drain terminal of low-side power MOSFET in the two-switch power stage of the DC-DC converter. Supply Input for the Gate-Driver of Internal Power MOSFETs. DRVIN is referenced to PGND. Bypass DRVIN with at least 0.1F to PGND. Connect DRVIN to REGOUT. High-Side Connection for the Isolation Transformer. Source connection of high-side power MOSFET in the two-switch power stage of the DC-DC converter. Drain Connection of High-Side MOSFET in the Two-Switch Power Stage of the DC-DC Converter. Connect DRNH to the most positive rail of the input supply. Bypass DRNH appropriately to handle the heavy switching current through the transformer. Boost Input for the DC-DC Converter. BST is the boost connection point for the high-side MOSFET driver. Connect a minimum 0.1F capacitor from BST to XFRMRH with short and wide PC board traces. DC-DC Converter Undervoltage Lockout Input. DCUVLO is referenced to GND. Connect a resistor-divider from HVIN to DCUVLO to GND to set the UVLO threshold. DC-DC Converter Positive Input Power Supply. HVIN is referenced to GND. Connect HVIN to V+. Input from the Rectified Bias Winding to the DC-DC Converter. INBIAS is referenced to GND. INBIAS is the input to the internal linear voltage regulator (REGOUT).
MAX5953A/MAX5953B/MAX5953C/MAX5953D
33, 34
DRNH
36
BST
37 39 40
DCUVLO HVIN INBIAS
41
Internal Regulator Output. REGOUT is used for the DC-DC converter gate driver. REGOUT is referenced to GND. VREGOUT is always present as long as HVIN is powered with a REGOUT voltage above the DCUVLO threshold. Bypass REGOUT to GND with a minimum 2.2F ceramic capacitor. Oscillator Frequency Set Input for the PWM Controller. RTCT is referenced to GND. Connect a resistor from RTCT to REGOUT and a ceramic capacitor from RTCT to GND to set the oscillator frequency. Fault Integration Input for PWM Controller. FLTINT is referenced to GND. During persistent current-limit faults, a capacitor connected to FLTINT is charged with an internal 80A current source. Switching is terminated when VFLTINT reaches 2.7V. An external resistor connected in parallel discharges the capacitor. Switching resumes when VFLTINT drops to 1.9V. Feed-Forward Input for PWM Controller. RCFF is referenced to GND. To generate the PWM ramp, connect a resistor from RCFF to HVIN and a capacitor from RCFF to GND. Ramp Sense Input for PWM Controller. Connect RAMP to RCFF. Exposed Paddle. EP is internally unconnected and must be connected to VEE externally. To improve power dissipation, solder the exposed paddle to a copper pad on the PC board.
42
RTCT
43
FLTINT
44 45 --
RCFF RAMP EP
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11
IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs MAX5953A/MAX5953B/MAX5953C/MAX5953D
Typical Application Circuit
POWER-OVER SIGNAL PAIRS 3 6 1 2 Rx
VREG
PHY
-48VRTN RJ-45 SGND Tx 4 5 7 8 -48V + + -
POWER-OVER SPAIR PAIRS
Figure 2. RJ-45 Connector, PoE Magnetic, and Input Diode Bridges
12
______________________________________________________________________________________
R17 14.7k
R16 316k
18 37 DCUVLO BST 31, 32 25T XFRMRL 8 RCLASS INBIAS D6 10 VEE RAMP RCFF REGOUT DRVIN GATE C15 1F 45 44 41 30 C4 4.7F C5 6800pF 16 OUT FLTINT RTCT 42 25 23 C9 220pF C8 0.1F C6 0.1F R9 1M C7 100pF 24 22 OPTO PGND R6 24.9k 43 CSS GND CS 20 SRC 26, 27 R10 100 R11 0.1 C16 0.15F R16 562 R14 143k E R8 OPEN PGND C10 0.33F R12 604 C *R1 AND R2 ARE OPTIONAL AND WHEN USED, THEY MUST TOTAL 25.5k AND REPLACE R3, 25.5k. LED FB U2 FOD2712 COMP GND C17 0.047F R15 16.2k 9 40 D3 R13 15 22T 28, 29 C12A 47F C12B 47F C11 0.1F D2 D4 36 HVIN DRNH PPWM PGOOD 4 V+ XFRMRH 6 UVLO C2 22F 63V R2* OPEN R4 (RRCLASS) 255 R1* OPEN
39
33, 34
21
Figure 3. Typical Application Circuit
OUT C13 0.1F
-48VRTN
D1 60V
C1 68nF
R3 (RDISC) 25.5k
MAX5953A
11T C14 0.0047F
SGND
-48V
R5 200k
C3 220pF
IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs
MAX5953A/MAX5953B/MAX5953C/MAX5953D
______________________________________________________________________________________
R7 1.78k
13
MAX5953A/MAX5953B/MAX5953C/MAX5953D
IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs
Figure 4. For higher power applications, the MAX5953A/MAX5953B/MAX5953C/MAX5953D can be used in a two-switch forward converter configuration
18 PGOOD 4 V+ XFRMRH 6 UVLO XFRMRL 8 RCLASS INBIAS RRCLASS 10 VEE RAMP RCFF REGOUT DRVIN GATE 45 44 41 30 9 40 28, 29 R2* 31, 32 R1* BST 36 DCUVLO HVIN DRNH PPWM 37 39 33, 34 21 VOUT
14
MAX5953A
SGND 16 OUT FLTINT RTCT 42 25 23 24 22 OPTO PGND 43 CSS GND CS 20 SRC 26, 27 E PGND LED FB U2 FOD2712 COMP C *R1 AND R2 ARE OPTIONAL AND WHEN USED, THEY MUST TOTAL 25.5k AND REPLACE R3, 25.5k. GND
-48VRTN
D1 60V
C1 68nF
R3 (RDISC) 25.5k
______________________________________________________________________________________
-48V
IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs
Detailed Description
PD Interface
The MAX5953A/MAX5953B/MAX5953C/MAX5953D include complete interface function for a PD to comply with the IEEE 802.3af standard in a PoE system. They provide the PD with a detection signature, a classification signature, and an integrated isolation switch with programmable inrush current control. An integrated MOSFET provides PD isolation during detection and classification. All devices guarantee a leakage current offset of less than 10A during the detection phase. A programmable current limit prevents high inrush current during power-on. The device features power-mode UVLO with wide hysteresis and long deglitch time to compensate for twisted-pair-cable resistive drop and to assure glitch-free transition between detection, classification, and power-on/-off phases. The MAX5953A/ MAX5953C have an adjustable UVLO threshold with the default value compliant to the 802.3af standard, while the MAX5953B/MAX5953D have a lower and fixed UVLO threshold compatible with some legacy pre-802.3af PSE.
Operating Modes
Depending on the input voltage (VIN = V+ - VEE), the PD front-end section of the MAX5953A/MAX5953B/ MAX5953C/MAX5953D operate in three different modes: PD detection signature, PD classification, and PD power. All voltage thresholds are designed to operate with or without the optional diode bridge while still complying with the IEEE 802.3af standard (see Figure 2). Detection Mode (1.4V VIN 10.1V) In detection mode, the power source equipment (PSE) applies two voltages on VIN in the range of 1.4V to 10.1V (1V step minimum), and records the corresponding current measurements at those two points. The PSE then computes V/I to ensure the presence of the 25.5k signature resistor. In this mode, most interface circuitry of the MAX5953A/MAX5953B/MAX5953C/MAX5953D is off and the offset current is less than 10A. Classification Mode (12.6V VIN 20V) In the classification mode, the PSE classifies the PD based on the power consumption required by the PD. This allows the PSE to efficiently manage power distribution. The IEEE 802.3af standard defines five different classes as shown in Table 1. An external resistor (RRCLASS) connected from RCLASS to VEE sets the classification current. The PSE determines the class of a PD by applying a voltage at the PD input and measuring the current sourced out of the PSE. When the PSE applies a voltage between 12.6V and 20V, the IC exhibits a current characteristic with values indicated in Table 2. The PSE uses the classification current information to classify the power requirement of the PD. The classification current includes the current drawn by the 25.5k detection signature resistor and the supply current of the IC so the total current drawn by the PD is within the IEEE 802.3af standard figures. The classification current is turned off whenever the device is in power mode.
MAX5953A/MAX5953B/MAX5953C/MAX5953D
Table 1. PD Power Classification/ RRCLASS Selection
CLASS 0 1 2 3 4 USAGE Default Optional Optional Optional Not Allowed RRCLASS () 10k 732 392 255 178 MAXIMUM POWER USED BY PD (W) 0.44 to 12.95 0.44 to 3.84 3.84 to 6.49 6.49 to 12.95 Reserved*
*Class 4 reserved for future use.
Table 2. Setting Classification Current
CLASS 0 1 2 3 4 RRCLASS () 10k 732 392 255 178 VIN* (V) 12.6 to 20 12.6 to 20 12.6 to 20 12.6 to 20 12.6 to 20 CLASS CURRENT SEEN AT VIN (mA) MIN 0 9.17 17.29 26.45 36.60 MAX 2.00 11.83 19.71 29.55 41.40 IEEE 802.3af PD CLASSIFICATION CURRENT SPECIFICATION (mA) MIN 0 9 17 26 36 MAX 4 12 20 30 44
*VIN is measured across the MAX5953A/MAX5953B/MAX5953C/MAX5953D input pins (V+ - VEE), which do not include the diode bridge voltage drop. ______________________________________________________________________________________ 15
IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs MAX5953A/MAX5953B/MAX5953C/MAX5953D
Power Mode During power mode, when VIN rises above the undervoltage lockout threshold (VUVLO,ON), the IC gradually turns on the internal n-channel MOSFET Q1 (see Figure 8). The IC charges the gate of Q1 with a constant current source (10A, typ). The drain-to-gate capacitance of Q1 limits the voltage rise rate at the drain of the MOSFET, thereby limiting the inrush current. To further reduce the inrush current, add external drain-to-gate capacitance (see the Inrush Current Limit section). When the drain of Q1 is within 1.2V of its source voltage and its gate-tosource voltage is above 5V, the MAX5953A/MAX5953B assert the PGOOD output (MAX5953C/MAX5953D assert the PGOOD output). The IC has a wide UVLO hysteresis and turn-off deglitch time to compensate for the high impedance of the twisted-pair cable. IINRUSH = IG x COUT CGATE
The recommended typical inrush current for a PoE application is 100mA.
PGOOD/PGOOD Output
PGOOD is an open-drain, active-high logic output. PGOOD goes high impedance when V OUT is within 1.2V of V EE and when GATE is 5V above V EE . Otherwise, PGOOD is pulled to VOUT (given that VOUT is at least 5V below V+). Connect PGOOD directly to CSS to enable/disable the DC-DC converter. PGOOD is an open-drain, active-low logic output. PGOOD is pulled to V EE when V OUT is within 1.2V of V EE and when GATE is 5V above VEE. Otherwise, PGOOD goes high impedance. Connect a 100k pullup resistor from PGOOD to V+ if needed.
Undervoltage Lockout for PD Interface
The IC operates up to a 67V supply voltage with a default UVLO turn-on (VUVLO,ON) set at 38.6V (MAX5953A/ MAX5953C) or 35.4V (MAX5953B/MAX5953D) and a UVLO turn-off (VUVLO,OFF) set at 30V. The MAX5953A/ MAX5953C have an adjustable UVLO threshold using a resistor-divider connected to UVLO (see Figure 3). When the input voltage goes below the UVLO threshold for more than tOFF_DLY, the MOSFET turns off. To adjust the UVLO threshold, connect an external resistor-divider from V+ to UVLO to VEE. Use the following equations to calculate R1 and R2 for a desired UVLO threshold: R2 = 25.5k x VREF,UVLO VIN,EX
Thermal Dissipation
Thermal shutdown limits total power dissipation in the IC. If the junction temperature exceeds +160C, thermal shutdown is enabled to turn off the MAX5953A/ MAX5953B/MAX5953C/MAX5953D, allowing the IC to cool. The IC turns on after the junction temperature cools by 20C.
DC-DC Converter
The MAX5953A/MAX5953B/MAX5953C/MAX5953D isolated PWM power ICs feature integrated switching power MOSFETs connected in a voltage-clamped, two-transistor, power-circuit configuration. These devices can be used in both forward and flyback configurations with a wide 11V to 76V input voltage range. The voltageclamped power topology enables full recovery of stored magnetizing and leakage inductive energy for enhanced efficiency and reliability. A look-ahead signal for driving secondary-side synchronous rectifiers can be used to increase efficiency. A wide array of protection features include UVLO, overtemperature shutdown, and short-circuit protection with hiccup current-limit for enhanced performance and reliability. Operation up to 500kHz allows smaller external magnetics and capacitors.
R1 = 25.5k - R2 where VIN,EX is the desired UVLO threshold. Since the resistor-divider replaces the 25.5k PD detection resistor, ensure that the sum of R1 and R2 equals 25.5k 1%. When using the external resistor-divider, MAX5953A/ MAX5953C have an external reference voltage hysteresis of 20% (typ). In other words, when UVLO is programmed externally, the turn-off threshold is 80% (typ) of the new UVLO threshold.
Inrush Current Limit
The IC charges the gate of the internal MOSFET with a constant current source (10A, typ). The drain-to-gate capacitance of the MOSFET limits the voltage rise rate at the drain, thereby limiting the inrush current. Add an external capacitor from GATE to OUT to further reduce the inrush current. Use the following equation to calculate the inrush current:
Power Topology
The two-switch forward-converter topology offers outstanding robustness against faults and transformer saturation while affording efficient use of 0.4 power MOSFETs. Voltage-mode control with feed-forward compensation allows the rejection of input supply disturbances within a single cycle similar to that of currentmode controlled topologies.
16
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IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs
The two-switch power topology recovers energy stored in both the magnetizing and the parasitic leakage inductances of the transformer. The Typical Application Circuit, Figure 3, shows the schematic diagram of a -48V input flyback converter using the MAX5953A. Figure 4 shows the schematic diagram of a -48V input forward converter and a 5V, 3A output isolated power supply. external resistive divider (R16 and R17) connected to DCUVLO (see Figure 3). Use the following equation to calculate R16 and R17: R16 VDCUVLOIN = VDCUVLO x 1 + R17 where VDCUVLOIN is the desired input voltage lockout level and VDCUVLO is the undervoltage lockout threshold (1.25V, typ). Select the R17 resistance value between 100k and 500k.
MAX5953A/MAX5953B/MAX5953C/MAX5953D
Voltage-Mode Control and the PWM Ramp
For voltage-mode control, the feed-forward PWM ramp is generated at RCFF. From RCFF, connect a capacitor to GND and a resistor to HVIN. The ramp generated is applied to the noninverting input of the PWM comparator at RAMP and has a minimum voltage of approximately 2V. The slope of the ramp is determined by the voltage at HVIN and affects the overall loop gain. The ramp peak must remain below the 5.5V dynamic range of RCFF. Assuming the maximum duty cycle approaches 50% at a minimum input voltage (PWM UVLO turnon threshold), use the following formula to calculate the minimum value of either the ramp capacitor or resistor: RRCFF x CRCFF VIN,EX 2 x fS x VR(P-P)
Optocoupled Feedback
Isolated voltage feedback is achieved by using an optocoupler as shown in Figure 3. Connect the collector of the optotransistor to OPTO and a pullup resistor between OPTO and REGOUT.
Internal Regulators
As soon as power is provided to HVIN, internal power supplies power the DCUVLO detection circuitry. REGOUT is used to drive the internal power MOSFETs. Bypass REGOUT to GND with a minimum 2.2F ceramic capacitor. The HVIN LDO steps down VHVIN to a nominal output voltage (VREGOUT) of 8.75V. A second parallel LDO powers REGOUT from INBIAS. A tertiary winding connected through a diode to INBIAS powers up REGOUT once switching commences. This powers REGOUT to 10.5V (typ) and shuts off the current flowing from HVIN to REGOUT. This results in a lower onchip power dissipation and higher efficiency.
where fS is the switching frequency, VR(P-P) is the peakto-peak ramp voltage (2V, typ). Select RRCFF resistance value between 200k and 600k. Maximize the signal-to-noise ratio by setting the ramp peak as high as possible. Calculate the low-frequency, small-signal gain of the power stage (the gain from the inverting input of the PWM comparator to the output) using the following formula: GPS = NSP x RRCFF x CRCFF x fS where NSP is the secondary to primary power transformer turns ratio.
Secondary-Side Synchronization
The MAX5953A/MAX5953B/MAX5953C/MAX5953D provide convenient synchronization for optional secondary-side synchronous rectifiers. Figure 5 shows the connection diagram with a high-speed optocoupler. Choose an optocoupler with a propagation delay of less than 80ns. The synchronizing pulse is generated approximately 110ns ahead of the main pulse that drives the two power MOSFETs.
MAX5953A MAX5953B MAX5953C MAX5953D
R PPWM
+5V
PGND C
Undervoltage Lockout for DC-DC Converter
Connect PGOOD to DCUVLO to ensure the PD interface is ready prior to the DC-DC converter. The DCUVLO block monitors the input voltage at HVIN through an
Figure 5. Secondary-Side Synchronous Rectifier Driver Using a High-Speed Optocoupler
______________________________________________________________________________________
17
IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs MAX5953A/MAX5953B/MAX5953C/MAX5953D
Soft-Start
Program the MAX5953A/MAX5953B/MAX5953C/ MAX5953D soft-start with an external capacitor (CCSS) connected between CSS and GND. When the device turns on, C CSS charges with a constant current of 33A, ramping up to 7.3V. During this time, the feedback input (OPTO) is clamped to VCSS + 0.6V. This initially holds the duty cycle lower than the value the regulator imposes, thus preventing voltage overshoot at the output. When the IC turns off, the soft-start capacitor internally discharges to GND. I xt CFLTINT FLTINT SH 1.4 where IFLTIN is typically 80A, and tSH is the desired ignore time during which current-limit events from the current-limit comparator are ignored. This is an approximate formula; some testing may be required to fine tune the actual value of the capacitor. Calculate the approximate bleed resistor needed for the desired recovery time using the following formula: RFLTINT tRT CFLTINT x 0.3514
Oscillator
The oscillator is externally programmable through a resistor connected from RTCT to REGOUT and a capacitor connected from RTCT to GND. The PWM frequency is one-half the frequency seen at RTCT with a 50% duty cycle. Use the following formula to calculate the oscillator components: RRTCT 1 VREGOUT 2fs (CRTCT + CPCB )In VREGOUT - VTH,RTCT
where tRT is the desired recovery time. Choose tRT 10 x tSH. Typical values for tSH can range from a few hundred microseconds to a few milliseconds.
Shutdown
Shut down the controller section of the IC by driving DCUVLO to GND using an open-collector or open-drain transistor connected to GND. The DC-DC converter section shuts down if REGOUT is below its DCUVLO level.
where CPCB is the stray capacitance on the PC board (14pF, typ), VTH,RTCT is the RTCT peak trip level, and fS is the switching frequency.
Current-Sense Comparator
The current-sense (CS) comparator and its associated logic limit the peak current through the internal MOSFET. Current is sensed at CS as a voltage across a sense resistor between the source of the MOSFET and GND. The power MOSFET switches off when the voltage at CS reaches 156mV. Select the current-sense resistor, RSENSE, according to the following equation: RSENSE = 0.156V / ILimPrimary where ILimPrimary is the maximum peak primary-side current. To reduce switching noise, connect CS to an external RC lowpass filter for additional filtering (Figure 3).
Integrating Fault Protection
The integrating fault protection feature allows the IC to ignore transient overcurrent conditions for a programmable amount of time, giving the power-supply time to behave like a current source to the load. This can happen, for example, under load-current transients when the control loop requests maximum current to keep the output voltage from going out of regulation. The ignore time is programmed externally by connecting a capacitor from FLTINT to GND. Under sustained overcurrent faults, the voltage across this capacitor ramps up toward the FLTINT shutdown threshold (2.7V, typ). When V FLTINT reaches the shutdown threshold, the power supply shuts down. A high-value bleed resistor connected in parallel with the FLTINT capacitor allows the capacitor to discharge toward the restart threshold (1.9V, typ). FLTINT drops to the restart threshold allowing for soft-starting the supply again. The fault integration circuit works by forcing an 80A current into FLTINT for one clock cycle every time the current-limit comparator ILIM (Figure 9) trips. Use the following formula to calculate the approximate capacitor needed for the desired shutdown time:
Applications Information
Design Example
Design Example 1: PD with three-output flyback DCDC converter Figure 6 shows an isolated three-output flyback DC-DC converter. It provides output voltages of 10V at 30mA, 5.1V at 1.8A, and 2.55V at 5.4A. Design Example 2: PD with nonisolated step-down (buck) converter Figure 7 shows a buck converter with 12V, 0.75A output. Caution: this converter does not have active current limit.
18
______________________________________________________________________________________
C25 0.1F G1 R6 100 D10 A1 G2 R17 14.7k PPWM D2 18 37 DCUVLO BST 31, 32 D4 R19 XFRMRL 8 RCLASS D12 A2 G1 N4 G2 C17A 100F C17 220F D6 10 VEE RAMP RCFF REGOUT DRVIN D7 GATE A2 16 OUT FLTINT RTCT 42 25 23 24 22 26, 27 C19 0.068F R10 0.18 R24 1k 3 C13 0.22F R11 2k R14 470 E R25 OPEN 2 8 LED U2 7 FOD2712 FB 6 COMP 5 C GND N.C. 1, 4 C20 0.068F R20 2.74k D8 20 OPTO PGND SRC VOUT2 R22 221 R9 1k R23 1M D5 A1 C21 0.1F R7 25.5k C7 0.01F C8 100pF C5 1000pF R8 1M C6 100pF 43 CSS CS GND C12 0.1F VOUT3 45 44 41 30 C3 2.2F 9 C4 4700pF C11 0.1F N2 N3 INBIAS 40 28, 29 A1 1k N1 C16 VOUT3 100pF VOUT2 C15 22F VOUT2 (5.1V AT 1.8A) C9 0.22F D11 T1 R18 22 36 R16 1k R17 22 HVIN DRNH PPWM D3 C14 0.47F PGOOD 4 V+ XFRMRH 6 UVLO C10 22F 63V R2* 0 R4 (RCL) 255 R5 210k R1* OPEN 39 33, 34 21 VOUT1 (10V AT 30mA) T2 PA0264 A2 R16 316k -48VOUT D9 C26 0.1F R27 10k PPWM C24 0.1F R28 10k
-48VRTN
D1 56.7V
C1 0.068F
R3 (RDISC) 25.5k
Figure 6. PD with Three-Output Flyback DC-DC Converter
U1
INBIAS VOUT3 (2.55V AT 5.4A)
MAX5953A
-48V
INBIAS R6 210k
-48VOUT C18 2200pF
RTN
R15 210k
C2 100pF
-48VOUT
C22 220F
C23 220F
GATE
R21 2.52k
IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs
MAX5953A/MAX5953B/MAX5953C/MAX5953D
______________________________________________________________________________________
*R1 AND R2 ARE OPTIONAL AND WHEN USED, THEY MUST TOTAL 25.5k AND REPLACE R3, 25.5k.
19
MAX5953A/MAX5953B/MAX5953C/MAX5953D
Figure 7. PD with Nonisolated Step-Down (Buck) Converter
PGOOD R9 14.7k R8 316k 18 PGOOD DCUVLO HVIN BST C10 0.022F XFRMRH 31, 32 L1 220H 36 OUT 12V, 0.75A DRNH PPWM 4 V+ 37 39 33, 34 21 C2 22F 63V 8 RCLASS R2 (RRCLASS) 255 XFRMRL 40 R7 3.9k 28, 29 D4 C11 22F C12 1F GND
IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs
20
U1
INBIAS 10 VEE
-48VRTN
D1 60V
C1 68nF
R1 (RDISC) 25.5k
0.5A
-48V 45 RAMP RCFF REGOUT DRVIN GATE C13 1F 44 41 30 C4 2.2F C5 4700pF 16 OUT FLTINT RTCT 42 25 23 24 22 PGOOD 20 OPTO PGND R4 26.7k 43 CSS CS GND SRC 26, 27 9
MAX5953A
R3 210k
C3 100pF
C6 150pF R6 100k C7 100pF
C8 0.022F
R13 14.3k C16 0.01F C9 OPEN PGND R10 OPEN TL431CD
R11 6.81k
C14 0.15F
R16 4.99k C15 0.03F
______________________________________________________________________________________
R5 1k R12 1.78k
IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs
Table 3. Component Suppliers
COMPONENT Power FETS Fairchild Vishay-Siliconix Current-Sense Resistors Dale-Vishay IRC ON Semi Diodes General Semiconductor Central Semiconductor Sanyo Capacitors Taiyo Yuden AVX Coiltronics Magnetics Coilcraft Pulse Engineering SUPPLIERS International Rectifier www.irf.com www.fairchildsemi.com www.vishay.com/brands/siliconix/main.html www.vishay.com/brands/dale/main.html www.irctt.com/pages/index.cfm www.onsemi.com www.gensemi.com www.centralsemi.com www.sanyo.com www.t-yuden.com www.avxcorp.com www.cooperet.com www.coilcraft.com www.pulseeng.com WEBSITE
MAX5953A/MAX5953B/MAX5953C/MAX5953D
Layout Recommendations
All connections carrying pulsed currents must be very short, as wide as possible, and have a ground plane as a return path. The inductance of these connections must be kept to a minimum due to the high di/dt of the currents in high-frequency-switching power converters.
Current loops must be analyzed in any layout proposed, and the internal area kept to a minimum to reduce radiated EMI. Ground planes must be kept as intact as possible.
______________________________________________________________________________________
21
IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs MAX5953A/MAX5953B/MAX5953C/MAX5953D
Block Diagrams
V+ UVLO V+ REF 2.4V REF EN 6.8V
CLASSIFICATION
RCLASS
21.8V
2.4V, 0.8 HYST
MAX5953A MAX5953B MAX5953C MAX5953D
PGOOD** Q4
39V
VGATE, 6V EN 1.2V, REF PGOOD*** 5V, REF Q3
UVLO*
200mV GATE
Q2 38 Q1 0.6
OUT
*MAX5953A/MAX5953C ONLY. **MAX5953C/MAX5953D ONLY. ***MAX5953A/MAX5953B ONLY.
VEE
Figure 8. Powered Device Interface Block Diagram
22
______________________________________________________________________________________
IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs
Block Diagrams (continued)
MAX5953A/MAX5953B/MAX5953C/MAX5953D
REGOK REGOUT REG OVT REFOK RCFF 1.25V 5V IFLT 80A Q D T R FLTINT RAMP 2.7V/1.9V OVRLD R Q GND 80ns DELAY LEVEL SHIFT 0.4 5V REF (1.25V)
INBIAS HVIN DCUVLO DCUVLO DCUVLO
PPWM 7.5V 50 BST DRNH QH XFRMRH S LEADINGEDGE DELAY CLK Q R T-FF T SHDN OSC 0.4 THERMAL SHUTDOWN OVT QL SRC PGND ONE SHOT 30 QB DRVIN XFRMRL
CPWM OPTO 5V
33A CSS
GND
50
OVT DCUVLO REFOK REGOK OVRLD GND ILIM 10MHz
RTCT CS
MAX5953A MAX5953B MAX5953C MAX5953D
150mV PGND
Figure 9. DC-DC Converter Block Diagram (Voltage-Mode PWM Controller and Two-Switch Power Stage)
______________________________________________________________________________________
23
MAX5953A/MAX5953B/MAX5953C/MAX5953D
IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs
24
18 PGOOD 4 V+ XFRMRH 6 UVLO XFRMRL 8 RCLASS 40 28, 29 R2* 31, 32 OUT R1* BST 36 DCUVLO HVIN DRNH PPWM 37 39 33, 34 21
-48VRTN
D1 60V
C1 68nF
R3 (RDISC) 25.5k
U1
INBIAS RRCLASS 10 VEE RAMP RCFF REGOUT DRVIN GATE 45 44 41 30 9
MAX5953A
SGND
-48V
16 OUT FLTINT RTCT 42 25 23 24 22 OPTO PGND 43 CSS GND CS 20
SRC 26, 27
E PGND
LED FB U2 FOD2712 COMP C GND
______________________________________________________________________________________
Typical Operating Circuit
*R1 AND R2 ARE OPTIONAL AND WHEN USED, THEY MUST TOTAL 25.5k AND REPLACE R3, 25.5k.
IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs
Pin Configuration
TOP VIEW
XFRMRH XFRMRH XFRMRL XFRMRL DRVIN DRNH DRNH OPTO N.C. SRC SRC BST
MAX5953A/MAX5953B/MAX5953C/MAX5953D
36 35 34 33 32 31 30 29 28 27 26 25 DCUVLO N.C. HVIN INBIAS REGOUT RTCT FLTINT RCFF RAMP N.C. N.C. N.C. 37 38 39 40 41 42 43 44 45 46 47 48 + 1 N.C. 2 N.C. 3 N.C. 4 V+ 5 N.C. 6 * 7 N.C. 8 RCLASS 9 GATE 10 11 12 N.C. VEE VEE 24 23 22 21 CSS PGND GND PPWM CS N.C. ** N.C. OUT OUT N.C. N.C.
MAX5953A MAX5953B MAX5953C MAX5953D
20 19 18 17 16 15 14 13
THIN QFN 7mm x 7mm
*UVLO FOR MAX5953A/MAX5953C N.C. FOR MAX5953B/MAX5953D ** PGOOD FOR MAX5953A/MAX5953B PGOOD FOR MAX5953C/MAX5953D
Selector Guide
PART MAX5953A MAX5953B MAX5953C MAX5953D PGOOD or PGOOD PGOOD PGOOD PGOOD PGOOD
Chip Information
PROCESS: BiCMOS
UVLO Adjustable Fixed Adjustable Fixed
______________________________________________________________________________________
25
IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs MAX5953A/MAX5953B/MAX5953C/MAX5953D
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
E E/2
DETAIL A
(NE-1) X e
k e D/2
D
(ND-1) X e
C L
D2
D2/2
b L E2/2 DETAIL B e L k
C L
E2
C L
C L
L1
L e e
L
A1
A2
A
PACKAGE OUTLINE 32, 44, 48, 56L THIN QFN, 7x7x0.8mm
21-0144
E
1
2
26
______________________________________________________________________________________
32, 44, 48L QFN.EPS
IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
MAX5953A/MAX5953B/MAX5953C/MAX5953D
PACKAGE OUTLINE 32, 44, 48, 56L THIN QFN, 7x7x0.8mm
21-0144
E
2
2
Revision History
Pages changed at Rev 1: 1, 27
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 27 (c) 2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
M. Quijano

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